Reduced Pressure Silicon Epitaxy
The silicon epitaxy process refers to the growth of a layer of single crystal material with the same lattice arrangement as the substrate on a single crystal substrate, Perfectus-R is mainly used for heteroepitaxial layers（SiGe/Si or SiP/Si）growth. It’s aimed at improving the mobility of electrons or holes in the CMOS process of logic chips, thereby improving device performance.
NMOS: Si Channel / Strained SiGe Source-Drain; PMOS: Strained SiGe Channel / SiGe Source-Drain; Channel Materials:Pure Si (for NMOS);
Strained SiGe (for PMOS); Pure Ge (Emerging Channel)
increased production capacity to 1.5 times, lower CoO
Optimized reaction chamber design aided by CFD simulation to achieve performance requirements such as WiW/WtW uniformity, doping uniformity and center-edge tunability
Suitable for Channel/NMOS/PMOS applications, excellent electrical properties and defect control
Top production stability, reliability and safety, multi-level hardware and software safety interlock testing
Excellent software operating system and intelligent data analysis platform, the world's top technology/hardware customer support team
